Technologies Available for Licensing
	Configurable Decoder for Pin-Limited Applications
	Category:	Computer Science
	LSU Reference:	0624
	Inventor:	Ramachandran Vaidyanathan and Matthew Collin Jordan
	Status:	Under patent prosecution
	Description:	Pin limitation is a major performance and size bottleneck in IC chips, including in FPGAs. This invention describes a configurable decoder which, for pin-limited environments, efficiently translates a limited number of input signals into a large number of output signals. In contrast to current approaches, this technology allows flexibility and re-configurablility, without incurring high costs in terms of performance impact, gate count and manufacturing expense. It also provides techniques for reducing gate count requirements of 1-hot decoder implementations. Obtain downloadable brochure here.
	Applications:	FPGA (field programmable gate array) design External power management Any pin-limited environment
	Advantages:	The current state of the art of decoders falls into two classes. A fixed decoder solution is low-cost but elementary, slow and inflexible. Solutions based on a look-up table (LUT) mapping are reconfigurable, but very expensive in terms of gate count. Our configurable decoder enables fast, economical yet flexible signal translation, by combining the cost-effectiveness of fixed decoder technology with the flexibility of LUT-based decoders. For companies who wish to retain fixed (1-hot) decoder technology, we also offer a design solution for fixed decoders which allows significant reduction in gate cost without much impact on speed and area.
	Abstract:	Pin limitations are a major performance and size bottleneck in IC chips, particularly in FPGAs. Most chips today therefore use fixed decoders, where a few (n) bits enter the chip and are internally decoded into a large number (N >> n) bits. Decoded bits are required quickly, so speed is an issue. Currently used 1-hot decoders select one element at a time, resulting in a slow overall solution when several elements need to be selected. An important way in which an FPGA adapts to the needs of an application is by changing configurations while the application is running. This typically involves selecting and configuring a subset of components of the FPGA. Thus, flexibility in selecting a set of output bit patterns that are tailored to the application at hand is an important issue as well. Solutions based on a look-up table (LUT) mapping are reconfigurable, but expensive in terms of gate count. Run-time/dynamic configuration, while being a powerful computational tool, is currently not as efficient as it could be in FPGAs as it requires large amounts of information to be input into the device from an external source. This innovative hybrid solution stages a fixed translation module with a secondary LUT-based module. The resultant configurable decoder enables fast, economical, yet flexible, operation.
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